Referring now to FIG. 1, a wireless transceiver 10 is shown and includes a transmitter 12 and a receiver 14. The wireless transceiver 10 may be used in a local area network (LAN) and may be attached to a Baseband Processor (BBP) and a Media Access Controller (MAC) in either a station or an Access Point (AP) configuration. A network interface card (NIC) is one of the various “STATION” configurations. The NIC can be connected to a networked device 16 such as a laptop computer, a personal digital assistant (PDA) or any other networked device. When the transceiver 10 is attached to an access point (AP) MAC, an AP is created. The AP provides network access for wireless local area network (WLAN) stations that are associated with the transceiver 10.
The wireless transceiver 10 transmits and receives frames/packets and provides communication between two networked devices. In AdHoc mode, the two devices can be two laptop/personal computers. In infrastructure mode, the two devices can be a laptop/personal computer and an AP.
There are multiple different ways of implementing the transmitter 12 and the receiver 14. For purposes of illustration, simplified block diagrams of super-heterodyne and direct conversion transmitter and receiver architectures will be discussed, although other architectures may be used. Referring now to FIG. 2A, an exemplary super-heterodyne receiver 14-1 is shown. The receiver 14-1 includes an antenna 19 that is coupled to an optional RF filter 20 and a low noise amplifier 22. An output of the amplifier 22 is coupled to a first input of a mixer 24. A second input of the mixer 24 is connected to an oscillator 25, which provides a reference frequency. The mixer 24 converts radio frequency (RF) signals to intermediate frequency (IF) signals.
An output of the mixer 24 is connected to an optional IF filter 26, which has an output that is coupled to an automatic gain control amplifier (AGCA) 32. An output of the AGCA 32 is coupled to first inputs of mixers 40 and 41. A second input of the mixer 41 is coupled to an oscillator 42, which provides a reference frequency. A second input of the mixer 40 is connected to the oscillator 42 through a −90° phase shifter 43. The mixers 40 and 41 convert the IF signals to baseband (BB) signals. Outputs of the mixers 40 and 41 are coupled to BB circuits 44-1 and 44-2, respectively. The BB circuits 44-1 and 44-2 may include low pass filters (LPF) 45-1 and 45-2 and gain blocks 46-1 and 46-2, respectively, although other BB circuits may be used. Mixer 40 generates an in-phase (I) signal, which is output to a BB processor 47. The mixer 41 generates a quadrature-phase (Q) signal, which is output to the BB processor 47.
Referring now to FIG. 2B, an exemplary direct conversion receiver 14-2 is shown. The receiver 14-2 includes the antenna 19 that is coupled the optional RF filter 20 and to the low noise amplifier 22. An output of the low noise amplifier 22 is coupled to first inputs of RF to BB mixers 48 and 50. A second input of the mixer 50 is connected to oscillator 51, which provides a reference frequency. A second input of the mixer 48 is connected to the oscillator 51 through a −90° phase shifter 52. The mixer 48 outputs the I-signal to the BB circuit 44-1, which may include the LPF 45-1 and the gain block 46-1. An output of the BB circuit 44-1 is input to the BB processor 47. Similarly, the mixer 50 outputs the Q signal to the BB circuit 44-2, which may include the LPF 45-2 and the gain block 46-2. An output of the BB circuit 44-2 is output to the BB processor 47.
Referring now to FIG. 3A, an exemplary super-heterodyne transmitter 12-1 is shown. The transmitter 12-1 receives an I signal from the BB processor 47. The I signal is input to a LPF 60 that is coupled to a first input of a BB to IF mixer 64. A Q signal of the BB processor 47 is input to a LPF 68 that is coupled to a first input of a BB to IF mixer 72. The mixer 72 has a second input that is coupled to an oscillator 74, which provides a reference frequency. The mixer 64 has a second input that is coupled to the oscillator through a −90° phase shifter 75.
Outputs of the mixers 64 and 72 are input to a summer 76. The summer 76 combines the signals into a complex signal that is input to a variable gain amplifier (VGA) 84. The VGA 84 is coupled to an optional IF filter 85. The optional IF filter 85 is connected to a first input of an IF to RF mixer 86. A second input of the mixer 86 is connected to an oscillator 87, which provides a reference frequency. An output of the mixer 86 is coupled to an optional RF filter 88. The optional RF filter 88 is connected to a power amplifier 89, which may include a driver. The power amplifier 89 drives an antenna 90 through an optional RF filter 91.
Referring now to FIG. 3B, an exemplary direct conversion transmitter 12-2 is shown. The transmitter 12-2 receives an I signal from the BB processor 47. The I signal is input to the LPF 60, which has an output that is coupled to a first input of a BB to RF mixer 92. A Q signal of the BB processor 47 is input to the LPF 68, which is coupled to a first input of a BB to RF mixer 93. The mixer 93 has a second input that is coupled to an oscillator 94, which provides a reference frequency. The mixer 92 has a second input that is connected to the oscillator 94 through a −90° phase shifter 95. Outputs of the mixers 92 and 93 are input to the summer 76. The summer 76 combines the signals into a complex signal that is input the power amplifier 89. The power amplifier 89 drives the antenna 90 through the optional RF filter 91. The RF and IF filters in FIGS. 2A, 2B, 3A and 3B may be implemented on-chip or externally.
Regardless of the architecture that is used, one of the primary functions performed by the transmitters and receivers is frequency conversion from BB to IF to RF and from RF to IF to BB. As described above, frequency conversion is performed in the mixers. Performance requirements of the mixers include conversion gain, noise and linearity.
In particular, mixer linearity is often a key parameter for systems with high performance requirements. In a receiver, mixer linearity affects the ability of the receiver to receive weak desired signals in the presence of strong adjacent-channel interference. In a transmitter, poor mixer linearity can cause excessive corruption in the transmitter spectrum and degrade signal integrity of the transmitter.
The mixers in the WLAN transceiver 10 can be implemented using Gilbert cell mixers. Referring now to FIG. 4A, a Gilbert Cell mixer 110 that is implemented using CMOS transistors according to the prior art is shown. The Gilbert cell mixer 110 includes a first stage 112 that performs voltage to current conversion or transconductor stage and a second stage 114 that performs frequency conversion.
The Gilbert cell mixer 110 includes a transconductor stage that is formed by a first transistor 122 and a second transistor 124. The transistors 122 and 124 have a source that is connected to a reference potential such as ground. A gate of the first transistor 122 is connected to one lead of a first voltage source. A gate of the second transistor 124 is connected to another lead of the first voltage source. The Gilbert cell mixer 110 further includes third, fourth, fifth, and sixth transistors 130, 132, 134, and 136. A drain of the first transistor 122 is coupled to sources of the third and fourth transistors 130 and 132. A drain of the second transistor 124 is coupled to sources of the fifth and sixth transistors 134 and 136.
A gate of the fourth transistor 132 is connected to a gate of the fifth transistor 134. The gates of the fourth and fifth transistors 132 and 134 are connected to a first lead of a second voltage source. Another lead of the second voltage source is connected to gates of the third and sixth transistors 130 and 136. A drain of the third transistor 130 is connected to a drain of the fifth transistor 134. A drain of the fourth transistor 132 is connected to a drain of the sixth transistor 136. Typically, the first voltage source is a radio frequency, intermediate frequency, or baseband signal requiring frequency conversion (up or down) and the second voltage source is a local oscillator.
When implemented in the form of FIG. 4A, linearity of the Gilbert cell mixer is typically limited by the bottom transconductance stage. Moreover, depending on the biasing scheme, the linearity performance will vary over temperature and process corners.